22 mpv5 series 9x14 mm, 5.0 volt, pecl, vcxo pin connections ? lvds and pecl output logic with good integrated jitter performance (5 ps) ? phase-locked loops (pll?s), clock recovery, reference signal tracking, synthesizers, frequency modulation/ demodulation
23 v c x o 1. frequencies above 70 mhz utilize a pll design. fundamental and pll designs are available for other frequencies. contact fac tory. 2. stability is given for deviation over temperature. 3. pecl load - see load circuit diagram #3 on page 148. 4. apr specification inclusive of initial tolerance, deviation over temperature, shock, vibration, supply voltage, and aging. mpv5 series 9x14 mm, 5.0 volt, pecl, vcxo
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